مهندس معماري نظم الأجهزة الرائد، منصة GPU (Hardware System Architect Lead, GPU Platform)

Job Summary

This role leads the architecture of Think AI’s multi-accelerator server platforms, including the design, validation, and production of high-density GPU systems with mixed silicon fabrics. The position involves overseeing platform development from initial design through manufacturing and quality assurance in Riyadh.

Responsibilities

• Manage end-to-end system architecture including CPU platform choice, PCIe Gen5/Gen6 topology, switch selection, lane budgeting, and GPU-to-NIC affinity across the chassis.
• Design for GPUDirect RDMA and peer-to-peer communication among heterogeneous accelerators, validating ACS, ATS, IOMMU, and P2P for each silicon vendor.
• Develop signal integrity strategies involving retimers, MCIO, cabled PCIe, risers, backplanes, and channel loss budgets, collaborating with layout and SI engineers.
• Lead power and thermal architecture for dense, high-TDP accelerator setups, coordinating with mechanical and thermal engineers on power delivery, airflow, and liquid cooling readiness.
• Define BIOS/UEFI and BMC requirements and collaborate with the ILM software team on hardware-software integration for bring-up, telemetry, firmware, and fabric.
• Write platform specifications and reference designs for JDM partners and oversee design reviews of schematics, layouts, and BOMs before release.
• Select and manage ODM and JDM partners for motherboards, chassis, and PCIe switches, driving platforms through EVT, DVT, and PVT to production at the Riyadh facility.
• Lead transition from JDM to in-house board design, owning schematics, layout, and SI/PI while maintaining PCB fabrication and assembly with partners, and plan future platform roadmaps.

Must haves

• 12+ years in hardware or system architecture focused on GPU-accelerated or accelerator-dense servers at an accelerator vendor, server OEM, ODM, or hyperscaler hardware team.
• Experience shipping at least one dense multi-GPU server platform from architecture through PVT into production.
• Deep expertise in PCIe including switch topologies, Gen5 and Gen6 signal integrity, retimers, enumeration, and BAR/resource allocation at scale.
• Strong knowledge of RDMA NICs, GPUDirect, NUMA, IOMMU, GPU-to-NIC communication, and power/thermal constraints in dense form factors.
• Ability to read schematics, lead layout reviews, and debug in lab environments using scopes and PCIe protocol analyzers.
• Hands-on experience with platform bring-up, validation, failure analysis from first power-on through production ramp, including factory debug at ODM or manufacturing sites.
• Experience writing validation plans, qualification matrices, and driving root cause analysis and corrective actions, with Python and Bash for test automation.
• Fluent English.

Nice to haves

• Hands-on schematic design experience for server motherboards, risers, or PCIe switch and retimer boards.
• Experience supporting multiple accelerator vendors on the same platform.
• Familiarity with open interconnect standards such as UALink, Ultra Ethernet (UEC), NVLink-class, and CXL.
• Experience with HGX, OAM, or UBB baseboards, OCP or ORv3 rack integration, liquid-cooled server design, DDR5 qualification, margin analysis, rack-level integration, reliability testing, or startup scaling.

What the company offers

• Competitive early-stage compensation.
• Meaningful ownership and impact at an early stage.
• Opportunity to work at one of the first deep tech companies in the region building foundational technology in-house.
• Close collaboration with a small, senior team.
• Challenging problems combining hardware, systems, and AI at scale.

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